FPGAs are not “programmed” in the sense we are used to, with a language like C, C ++, or Python. In fact, FPGAs use a different type of language called a descriptive language, rather than a programming language. These descriptive languages are called HDL (Hardware Description Language). We mostly hear of Verilog (HDL) as it is an open source platform.
Descriptive languages are not unique to FPGAs. On the contrary, they are an extremely useful tool in chip and SoC design. Subsequently, the integrator translates the description that we have made of the device into a synthesizable device with the FPGA blocks, and determines the connections that it has to make. The FPGA interprets the bit stream and configures the connections. From that moment on, the FPGA is configured with the circuit that we have defined.
HDL languages have a difficult learning curve
The biggest difficulty is that it has a very low degree of abstraction since they describe electronic circuits. This makes projects grow enormously as code grows. Manufacturers provide commercial tools for programming their own FPGAs. Nowadays, they configure complete environments with a large number of tools and functionalities. Unfortunately, most are not free and they are tied to the architecture of a single manufacturer. With the development of FPGAs, other languages have appeared that allow a higher level of abstraction, similar to C, Java, Mat lab. Finally, some initiatives have tried to convert from a programming language to HDL, which can then be loaded into the FPGA with its tools.
Why do you have to simulate an FPGA?
When we program a processor, if we make a mistake there are usually no serious problems. Usually we will even have an environment where we can Debug and trace the program, define breakpoints, and see the flow of the program. However, when programming an FPGA module we are physically configuring a system and we could cause a short circuit and damage part or all of the FPGA. For that reason, we will always simulate the design to be tested before loading it into the real FPGA. For the simulation, descriptive languages are used, in combination with some software that allows simulating and graphing the response of the FPGA.
How powerful is an FPGA?
It is difficult to define the computing power of an FPGA since it is something totally different from a processor like the one we can find in an Arduino, an STM32, an ESP8266, or even a computer like Raspberry PI. FPGAs excel at performing tasks in parallel, and for extremely fine control of time and synchronism of tasks. Actually, it is better to think in terms of an integrated circuit. Once programmed, the FPGA physically constitutes a circuit. In general, as we have discussed, an FPGA is slower than the equivalent ASIC.
The power of an FPGA is determined by the number of blocks available and the speed of its electronics. Other factors intervene such as the constitution of each of the blocks, and other elements such as the RAM blocks or PLLs. FPGAs normally incorporate a clock for the development of synchronous tasks.
